1. Field of the Invention
The present invention relates to an electronic component packaging structure with semiconductors and passive components built therein and a method for producing the same. The present invention further relates to an electronic component packaging structure that allows circuit boards to be electrically-connected minutely and a method for producing the same.
2. Related Background Art
In recent years, with a demand for high-performance and compact electronic equipment, semiconductor packages with still higher density and higher functionality have been demanded. Furthermore, in order to mount such a semiconductor package, compact and high-density circuit boards also are demanded.
Since a conventional glass epoxy board that utilizes a through hole structure formed with a drill is becoming incapable of coping with higher-density packaging, circuit boards capable of inner via hole connection are now being developed energetically in lieu of the conventional glass epoxy multilayer board (See U.S. Pat. No. 5,481,795 (FIG. 7), for example).
However, in fact, it is the current state that even the high-density packaging board with the inner via structure does not keep up with finer design rules on semiconductors. Specifically, although a pitch of lead-out electrodes is made finer to about 50 μm in accordance with finer wirings of a semiconductor, a pitch of wirings and a pitch of vias of a circuit board are still about 100 μm, and therefore a space for leading-out of the electrodes from the semiconductor becomes large. This factor impairs the miniaturization of a semiconductor package.
Meanwhile, as a configuration for coping with the miniaturization of the semiconductor, a chip size package (CSP) is proposed (See H06(1994)-224259 A (FIG. 1), for example). According to the configuration disclosed in H06(1994)-224259 A, a semiconductor package is flip-chip bonded on a circuit board, and further a grid-form electrode is formed two-dimensionally on a lower face of the circuit board, thus widening a pitch of connection electrodes. The grid-form electrode has a structure such that electrodes with a pitch of 100 μm or less, on which a semiconductor is flip-chip bonded, are led out in a grid form through the via connection in a circuit board called an interposer. This configuration enables a pitch of lead-out electrodes of about 0.5 to 1.0 mm. As a result, there is no need to make the circuit board for mounting the CSP so fine, and a low cost circuit board can be used. In addition, the use of the CSP has an advantage of allowing the resulting configuration to be treated like a semiconductor package whose reliability has been examined and ensured, as compared with the handling of a semiconductor bare chip. As a result, the cost required for broken chips, examination of faulty elements and securing the reliability can be reduced, as compared with the bare-chip technique in which a semiconductor is directly mounted on a circuit board. Moreover the package can be miniaturized, which is an advantage of the bare chip mounting.
As a result of the development of such a CSP, a semiconductor package is becoming smaller in size. However, with the development of the Internet, these is a demand for further smaller equipment such as a mobile personal computer that allows information to be dealt with personally and information terminals typified by mobile phones. In the light of the demand for smaller equipment, the miniaturization of semiconductor packages and the miniaturization of circuit boards approach their limits, and it becomes difficult for the conventional configuration for packaging components on the circuit board to realize further smaller and higher-density package. This is because, even when a pitch of the connection terminals of a semiconductor package is narrowed, there is a limit on the miniaturization of a wiring pattern of a circuit board, and a circuit board with a more multilayered configuration has to be used for mounting the narrowed-pitch semiconductor package, thus increasing the cost for the packaging.
To cope with these problems, a method for realizing a multilayered configuration using a circuit board at a low cost and a three-dimensional packaging configuration for embedding a component such as a semiconductor in a board are proposed. Further, a proposal is made for connecting such circuit boards mutually for the still higher density packaging (See U.S. Pat. No. 5,484,647 (FIG. 5), for example). U.S. Pat. No. 5,484,647 discloses that a prepreg having an inner via structure using a conductive paste is sandwiched between circuit boards and hot pressing is applied thereto, whereby a multilayered configuration can be realized with efficiency.
Furthermore, as the three-dimensional packaging configuration, for example, a proposal is made for achieving still higher density by embedding a semiconductor and a chip component in a board (See U.S. Pat. No. 6,038,133 (FIG. 4) and JP 2002-280713 A, for example). U.S. Pat. No. 6,038,133 and JP 2002-280713 A show an example where a semiconductor and a chip component are formed in a board so as to realize a multilayered configuration.
Furthermore, JP H08(1996)-340021 A proposes a technology for attaching a wiring film on a surface of a semiconductor chip with an adhesive.
As described above, efforts to make a semiconductor package smaller and to narrow its pitch approach their limits, and therefore further miniaturization thereof requires an increase in cost for packaging and an expensive circuit board.
Meanwhile, as for the conventional example in which hot pressing is applied to low-cost circuit boards using a prepreg having an inner via structure so as to form a multilayered configuration of the circuit boards, this example is only for enabling the multilayered configuration and not for obtaining a minute wiring pattern. Furthermore, in the case where the circuit board is manufactured in a large sheet form, followed by division into the individual pieces so as to reduce a cost for the mass production, a large scale apparatus is required conversely for manufacturing the circuit board, which means that a cost will be increased for the multilayered structure as a package or a module. Therefore, this is not suitable for the mass production. Furthermore, in the hot pressing method, a heating and curing process at about 180° C. for 1 hour or more is required, which leads to a problem of a process time becoming longer.
Furthermore, in the case of a component built-in board having a three-dimensional packaging configuration, already-existing semiconductors and passive components can be built therein. Therefore, such a board has an advantage of allowing even the conventional circuit board to be packaged with higher density. However, when the components are embedded in the circuit board, a long process time is required as described above, and moreover if there is a malfunction found in an examination after the embedding operation, the component cannot be exchanged.
Meanwhile, as the means for connecting a module on which components are packaged with a circuit board, there is a connector connection method available. However, the connector itself is large in size and a space is required for mounting the connector on a mother board, which becomes an obstacle to high-density packaging.